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Changeset 84

Timestamp:

10/23/06 23:07:11 (2 years ago)

Author:

vladest

Message:

SB code update
HDA code update
Some other updates

Location:

GPL/trunk

Files:

: 34 modified

alsa-kernel/core/control.c (modified) (6 diffs)
alsa-kernel/core/misc.c (modified) (2 diffs)
alsa-kernel/include/sound/asound.h (modified) (3 diffs)
alsa-kernel/include/sound/control.h (modified) (4 diffs)
alsa-kernel/include/sound/emu10k1.h (modified) (9 diffs)
alsa-kernel/pci/ca0106/ca0106_mixer.c (modified) (2 diffs)
alsa-kernel/pci/emu10k1/emu10k1.c (modified) (6 diffs)
alsa-kernel/pci/emu10k1/emu10k1_callback.c (modified) (6 diffs)
alsa-kernel/pci/emu10k1/emu10k1_main.c (modified) (31 diffs)
alsa-kernel/pci/emu10k1/emu10k1_patch.c (modified) (3 diffs)
alsa-kernel/pci/emu10k1/emu10k1_synth.c (modified) (4 diffs)
alsa-kernel/pci/emu10k1/emu10k1x.c (modified) (22 diffs)
alsa-kernel/pci/emu10k1/emufx.c (modified) (84 diffs)
alsa-kernel/pci/emu10k1/emumixer.c (modified) (45 diffs)
alsa-kernel/pci/emu10k1/emumpu401.c (modified) (3 diffs)
alsa-kernel/pci/emu10k1/emupcm.c (modified) (9 diffs)
alsa-kernel/pci/emu10k1/io.c (modified) (7 diffs)
alsa-kernel/pci/emu10k1/irq.c (modified) (1 diff)
alsa-kernel/pci/emu10k1/memory.c (modified) (7 diffs)
alsa-kernel/pci/emu10k1/p16v.c (modified) (29 diffs)
alsa-kernel/pci/emu10k1/voice.c (modified) (3 diffs)
alsa-kernel/pci/hda/hda_intel.c (modified) (1 diff)
alsa-kernel/pci/trident/trident_main.c (modified) (1 diff)
alsa-kernel/pci/ymfpci/ymfpci_main.c (modified) (1 diff)
drv32/dispatch.c (modified) (1 diff)
drv32/init.c (modified) (1 diff)
drv32/strategy.c (modified) (3 diffs)
include/ossdefos2.h (modified) (1 diff)
include/version.mak (modified) (1 diff)
lib32/irq.c (modified) (3 diffs)
lib32/ossidc.cpp (modified) (1 diff)
lib32/sound.c (modified) (6 diffs)
lib32/soundmixer.c (modified) (4 diffs)
lib32/stack.cpp (modified) (1 diff)

Legend:

: Unmodified
: Added
: Removed

GPL/trunk/alsa-kernel/core/control.c

r77	r84
27	27	/* max number of user-defined controls */
28	28	#define MAX_USER_CONTROLS 32
29
30		~~static inline struct snd_ctl_elem_id snd_ctl_build_ioff(struct snd_ctl_elem_id dst_id,~~
31		~~struct snd_kcontrol *src_kctl,~~
32		~~unsigned int offset)~~
33		{
34		*dst_id = src_kctl->id;
35		~~dst_id->index += offset;~~
36		~~dst_id->numid += offset;~~
37		~~return dst_id;~~
38		}
39	29
40	30	extern int control_id_changed;
…	…
223	213	* Returns the pointer of the newly generated instance, or NULL on failure.
224	214	*/
225		struct snd_kcontrol snd_ctl_new1(struct snd_kcontrol_new const ncontrol, void *private_data)
	215	struct snd_kcontrol snd_ctl_new1(struct snd_kcontrol_new const ncontrol,
	216	void *private_data)
226	217	{
227	218	struct snd_kcontrol kctl;
…	…
244	235	kctl.get = ncontrol->get;
245	236	kctl.put = ncontrol->put;
246		kctl.tlv = ncontrol->tlv;
	237	kctl.tlv.p =
	238	ncontrol->tlv.p;
247	239	kctl.private_value = ncontrol->private_value;
248	240	kctl.private_data = private_data;
…	…
1037	1029	#endif
1038	1030
1039		static int snd_ctl_tlv_read(struct snd_card *card,
1040		struct snd_ctl_tlv __user *_tlv)
1041		{
1042		struct snd_ctl_tlv tlv;
1043		struct snd_kcontrol *kctl;
1044		unsigned int len;
1045		int err = 0;
1046
1047		if (copy_from_user(&tlv, _tlv, sizeof(tlv)))
1048		return -EFAULT;
1049		if (tlv.length < sizeof(unsigned int) * 3)
1050		return -EINVAL;
1051		down_read(&card->controls_rwsem);
1052		kctl = snd_ctl_find_numid(card, tlv.numid);
1053		if (kctl == NULL) {
1054		err = -ENOENT;
1055		goto __kctl_end;
1056		}
1057		if (kctl->tlv == NULL) {
1058		err = -ENXIO;
1059		goto __kctl_end;
1060		}
1061		len = kctl->tlv[1] + 2 * sizeof(unsigned int);
1062		if (tlv.length < len) {
1063		err = -ENOMEM;
1064		goto __kctl_end;
1065		}
1066		if (copy_to_user(_tlv->tlv, kctl->tlv, len))
1067		err = -EFAULT;
1068		__kctl_end:
1069		up_read(&card->controls_rwsem);
1070		return err;
1071		}
	1031	static int snd_ctl_tlv_ioctl(struct snd_ctl_file *file,
	1032	struct snd_ctl_tlv __user *_tlv,
	1033	int op_flag)
	1034	{
	1035	struct snd_card *card = file->card;
	1036	struct snd_ctl_tlv tlv;
	1037	struct snd_kcontrol *kctl;
	1038	struct snd_kcontrol_volatile *vd;
	1039	unsigned int len;
	1040	int err = 0;
	1041
	1042	if (copy_from_user(&tlv, _tlv, sizeof(tlv)))
	1043	return -EFAULT;
	1044	if (tlv.length < sizeof(unsigned int) * 3)
	1045	return -EINVAL;
	1046	down_read(&card->controls_rwsem);
	1047	kctl = snd_ctl_find_numid(card, tlv.numid);
	1048	if (kctl == NULL) {
	1049	err = -ENOENT;
	1050	goto __kctl_end;
	1051	}
	1052	if (kctl->tlv.p == NULL) {
	1053	err = -ENXIO;
	1054	goto __kctl_end;
	1055	}
	1056	vd = &kctl->vd[tlv.numid - kctl->id.numid];
	1057	if ((op_flag == 0 && (vd->access & SNDRV_CTL_ELEM_ACCESS_TLV_READ) == 0) \|\|
	1058	(op_flag > 0 && (vd->access & SNDRV_CTL_ELEM_ACCESS_TLV_WRITE) == 0) \|\|
	1059	(op_flag < 0 && (vd->access & SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND) == 0)) {
	1060	err = -ENXIO;
	1061	goto __kctl_end;
	1062	}
	1063	if (vd->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
	1064	if (file && vd->owner != NULL && vd->owner != file) {
	1065	err = -EPERM;
	1066	goto __kctl_end;
	1067	}
	1068	err = kctl->tlv.c(kctl, op_flag, tlv.length, _tlv->tlv);
	1069	if (err > 0) {
	1070	up_read(&card->controls_rwsem);
	1071	snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_TLV, &kctl->id);
	1072	return 0;
	1073	}
	1074	} else {
	1075	if (op_flag) {
	1076	err = -ENXIO;
	1077	goto __kctl_end;
	1078	}
	1079	len = kctl->tlv.p[1] + 2 * sizeof(unsigned int);
	1080	if (tlv.length < len) {
	1081	err = -ENOMEM;
	1082	goto __kctl_end;
	1083	}
	1084	if (copy_to_user(_tlv->tlv, kctl->tlv.p, len))
	1085	err = -EFAULT;
	1086	}
	1087	__kctl_end:
	1088	up_read(&card->controls_rwsem);
	1089	return err;
	1090	}
	1091
1072	1092
1073	1093	static int snd_ctl_ioctl(struct inode inode, struct file file,
…	…
1093	1113	case SNDRV_CTL_IOCTL_ELEM_INFO:
1094	1114	return snd_ctl_elem_info(ctl, (struct snd_ctl_elem_info *) arg);
1095		~~#if 1~~
1096	1115	case SNDRV_CTL_IOCTL_ELEM_READ:
1097	1116	return snd_ctl_elem_read_user(ctl->card, argp);
1098	1117	case SNDRV_CTL_IOCTL_ELEM_WRITE:
1099	1118	return snd_ctl_elem_write_user(ctl, argp);
1100		~~#else~~
1101		~~case SNDRV_CTL_IOCTL_ELEM_READ:~~
1102		~~return snd_ctl_elem_read(ctl->card, (struct snd_ctl_elem_value *) arg);~~
1103		~~case SNDRV_CTL_IOCTL_ELEM_WRITE:~~
1104		~~return snd_ctl_elem_write(ctl, (struct snd_ctl_elem_value *) arg);~~
1105		~~#endif~~
1106	1119	case SNDRV_CTL_IOCTL_ELEM_LOCK:
1107	1120	return snd_ctl_elem_lock(ctl, (struct snd_ctl_elem_id *) arg);
…	…
1117	1130	return snd_ctl_subscribe_events(ctl, (int *) arg);
1118	1131	case SNDRV_CTL_IOCTL_TLV_READ:
1119		return snd_ctl_tlv_read(card, argp);
	1132	return snd_ctl_tlv_ioctl(ctl, argp, 0);
	1133	case SNDRV_CTL_IOCTL_TLV_WRITE:
	1134	return snd_ctl_tlv_ioctl(ctl, argp, 1);
	1135	case SNDRV_CTL_IOCTL_TLV_COMMAND:
	1136	return snd_ctl_tlv_ioctl(ctl, argp, -1);
1120	1137	case SNDRV_CTL_IOCTL_POWER:
1121	1138	if (get_user(err, (int *)arg))

GPL/trunk/alsa-kernel/core/misc.c

r34	r84
21	21
22	22	#include <sound/driver.h>
23
	23	#include <sound/firmware.h>
24	24	int snd_task_name(struct task_struct task, char name, size_t size)
25	25	{
…	…
669	669	}
670	670
	671	int mod_firmware_load(const char fn, char *fp)
	672	{
	673	return 0;
	674	}
	675
	676	static int snd_try_load_firmware(const char path, const char name,
	677	struct firmware *firmware)
	678	{
	679	char filename[30 + FIRMWARE_NAME_MAX];
	680
	681	sprintf(filename, "%s/%s", path, name);
	682	firmware->size = mod_firmware_load(filename, (char **)&firmware->data);
	683	if (firmware->size)
	684	printk(KERN_INFO "Loaded '%s'.", filename);
	685	return firmware->size;
	686	}
	687
	688	int request_firmware(const struct firmware *fw, const char name)
	689	{
	690	struct firmware *firmware;
	691
	692	*fw = NULL;
	693	firmware = kmalloc(sizeof *firmware, GFP_KERNEL);
	694	if (!firmware)
	695	return -ENOMEM;
	696	if (!snd_try_load_firmware("/lib/firmware", name, firmware) &&
	697	!snd_try_load_firmware("/lib/hotplug/firmware", name, firmware) &&
	698	!snd_try_load_firmware("/usr/lib/hotplug/firmware", name, firmware)) {
	699	kfree(firmware);
	700	return -EIO;
	701	}
	702	*fw = firmware;
	703	return 0;
	704	}
	705
	706	void release_firmware(const struct firmware *fw)
	707	{
	708	if (fw) {
	709	vfree(fw->data);
	710	kfree(fw);
	711	}
	712	}
	713

GPL/trunk/alsa-kernel/include/sound/asound.h

r77	r84
754	754	#define SNDRV_CTL_ELEM_ACCESS_VOLATILE (1<<2) /* control value may be changed without a notification */
755	755	#define SNDRV_CTL_ELEM_ACCESS_TIMESTAMP (1<<2) /* when was control changed */
	756	#define SNDRV_CTL_ELEM_ACCESS_TLV_READ (1<<4) /* TLV read is possible */
	757	#define SNDRV_CTL_ELEM_ACCESS_TLV_WRITE (1<<5) /* TLV write is possible */
	758	#define SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE (SNDRV_CTL_ELEM_ACCESS_TLV_READ\|SNDRV_CTL_ELEM_ACCESS_TLV_WRITE)
	759	#define SNDRV_CTL_ELEM_ACCESS_TLV_COMMAND (1<<6) /* TLV command is possible */
756	760	#define SNDRV_CTL_ELEM_ACCESS_INACTIVE (1<<8) /* control does actually nothing, but may be updated */
757	761	#define SNDRV_CTL_ELEM_ACCESS_LOCK (1<<9) /* write lock */
758	762	#define SNDRV_CTL_ELEM_ACCESS_OWNER (1<<10) /* write lock owner */
	763	#define SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK (1<<28) /* kernel use a TLV callback */
759	764	#define SNDRV_CTL_ELEM_ACCESS_USER (1<<29) /* user space element */
760	765	#define SNDRV_CTL_ELEM_ACCESS_DINDIRECT (1<<30) /* indirect access for matrix dimensions in the info structure */
…	…
864	869	SNDRV_CTL_IOCTL_ELEM_REMOVE = _IOWR('U', 0x19, struct snd_ctl_elem_id),
865	870	SNDRV_CTL_IOCTL_TLV_READ = _IOWR('U', 0x1a, struct snd_ctl_tlv),
	871	SNDRV_CTL_IOCTL_TLV_WRITE = _IOWR('U', 0x1b, struct snd_ctl_tlv),
	872	SNDRV_CTL_IOCTL_TLV_COMMAND = _IOWR('U', 0x1c, struct snd_ctl_tlv),
866	873	SNDRV_CTL_IOCTL_HWDEP_NEXT_DEVICE = _IOWR('U', 0x20, int),
867	874	SNDRV_CTL_IOCTL_HWDEP_INFO = _IOR('U', 0x21, struct snd_hwdep_info),
…	…
893	900	#define SNDRV_CTL_EVENT_MASK_INFO (1<<1) /* element info was changed */
894	901	#define SNDRV_CTL_EVENT_MASK_ADD (1<<2) /* element was added */
	902	#define SNDRV_CTL_EVENT_MASK_TLV (1<<3) /* element TLV tree was changed */
895	903	#define SNDRV_CTL_EVENT_MASK_REMOVE (~0U) /* element was removed */
896	904

GPL/trunk/alsa-kernel/include/sound/control.h

r77	r84
28	28	typedef int (snd_kcontrol_get_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol);
29	29	typedef int (snd_kcontrol_put_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol);
	30	typedef int (snd_kcontrol_tlv_rw_t)(struct snd_kcontrol *kcontrol,
	31	int op_flag, /* 0=read,1=write,-1=command */
	32	unsigned int size,
	33	unsigned int __user *tlv);
30	34
31	35	struct snd_kcontrol_new {
…	…
40	44	snd_kcontrol_get_t *get;
41	45	snd_kcontrol_put_t *put;
42		unsigned int *tlv;
	46	union {
	47	snd_kcontrol_tlv_rw_t *c;
	48	unsigned int *p;
	49	} tlv;
43	50	unsigned long private_value;
44	51	};
…	…
57	64	snd_kcontrol_get_t *get;
58	65	snd_kcontrol_put_t *put;
59		unsigned int *tlv;
	66	union {
	67	snd_kcontrol_tlv_rw_t *c;
	68	unsigned int *p;
	69	} tlv;
60	70	unsigned long private_value;
61	71	#ifdef TARGET_OS2
…	…
140	150	}
141	151
	152	static inline struct snd_ctl_elem_id snd_ctl_build_ioff(struct snd_ctl_elem_id dst_id,
	153	struct snd_kcontrol *src_kctl,
	154	unsigned int offset)
	155	{
	156	*dst_id = src_kctl->id;
	157	dst_id->index += offset;
	158	dst_id->numid += offset;
	159	return dst_id;
	160	}
	161
142	162	#endif /* __CONTROL_H */

GPL/trunk/alsa-kernel/include/sound/emu10k1.h

r34	r84
188	188	/* NOTE: The rest of the bits in this register */
189	189	/* _are_ relevant under Linux. */
190		#define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
	190	#define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
	191	#define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
	192	#define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
	193	#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
	194
	195	/* Specific to Alice2, CA0102 */
	196	#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
	197	#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
	198	#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
	199	/* will automatically mute their output when */
	200	/* they are not rate-locked to the external */
	201	/* async audio source */
	202	#define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
	203	/* will automatically mute their output when */
	204	/* the SPDIF V-bit indicates invalid audio */
	205	#define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
	206	#define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
	207	/* 0x00000800 not used on Alice2 */
	208	#define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
	209	/* phase track the previous input. */
	210	/* I2S0 can phase track the last S/PDIF input */
	211	#define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
	212	/* conversion for the corresponding */
	213	/* I2S format input */
	214	/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
	215
	216
	217
	218	/* Older chips */
191	219	#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
192	220	#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
…	…
245	273	#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
246	274	#define A_IOCFG_ENABLE_DIGITAL 0x0004
	275	#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
247	276	#define A_IOCFG_UNKNOWN_20 0x0020
248	277	#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
…	…
885	914	#define A_HIWORD_OPA_MASK 0x000007ff
886	915
	916	/************************************************************************************************/
	917	/* EMU1010m HANA FPGA registers */
	918	/************************************************************************************************/
	919	#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
	920	#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
	921	#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
	922	#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
	923	#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
	924	#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
	925	#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
	926	/* Must be written after power on to reset DLL */
	927	/* One is unable to detect the Audio dock without this */
	928	#define EMU_HANA_WCLOCK_SRC_MASK 0x07
	929	#define EMU_HANA_WCLOCK_INT_48K 0x00
	930	#define EMU_HANA_WCLOCK_INT_44_1K 0x01
	931	#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
	932	#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
	933	#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
	934	#define EMU_HANA_WCLOCK_2ND_HANA 0x05
	935	#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
	936	#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
	937	#define EMU_HANA_WCLOCK_MULT_MASK 0x18
	938	#define EMU_HANA_WCLOCK_1X 0x00
	939	#define EMU_HANA_WCLOCK_2X 0x08
	940	#define EMU_HANA_WCLOCK_4X 0x10
	941	#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
	942
	943	#define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
	944	#define EMU_HANA_DEFCLOCK_48K 0x00
	945	#define EMU_HANA_DEFCLOCK_44_1K 0x01
	946
	947	#define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
	948	#define EMU_MUTE 0x00
	949	#define EMU_UNMUTE 0x01
	950
	951	#define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
	952	#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
	953	#define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
	954
	955	#define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
	956	#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
	957	#define EMU_HANA_IRQ_ADAT 0x02
	958	#define EMU_HANA_IRQ_DOCK 0x04
	959	#define EMU_HANA_IRQ_DOCK_LOST 0x08
	960
	961	#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
	962	#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
	963	#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
	964	#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
	965	#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
	966	#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
	967	#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
	968	#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
	969
	970	#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
	971	#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
	972	#define EMU_HANA_OPTICAL_IN_ADAT 0x01
	973	#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
	974	#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
	975
	976	#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
	977	#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
	978	#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
	979
	980	#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
	981	#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
	982	#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
	983	#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
	984	#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
	985
	986	#define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
	987	#define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
	988	#define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
	989	#define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
	990	#define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
	991	#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
	992	#define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
	993
	994	#define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
	995	#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
	996	#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
	997	#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
	998	#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
	999	#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
	1000	#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
	1001
	1002	#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
	1003	#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
	1004	#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
	1005	#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
	1006	#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
	1007
	1008	#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
	1009	#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
	1010	#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
	1011	#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
	1012	#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
	1013	#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
	1014	#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
	1015	#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
	1016	#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
	1017
	1018	#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
	1019	#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
	1020	#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
	1021	#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
	1022	#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
	1023	#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
	1024
	1025	#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
	1026	#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
	1027	#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
	1028	#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
	1029	#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
	1030	#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
	1031
	1032	/* 0x14 - 0x1f Unused R/W registers */
	1033	#define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
	1034	#if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
	1035	#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
	1036	#define EMU_HANA_IRQ_ADAT 0x02
	1037	#define EMU_HANA_IRQ_DOCK 0x04
	1038	#define EMU_HANA_IRQ_DOCK_LOST 0x08
	1039	#endif
	1040
	1041	#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
	1042	#define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
	1043	#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
	1044	#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
	1045	#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
	1046
	1047	#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
	1048
	1049	#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
	1050	#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
	1051
	1052	#define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
	1053	#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
	1054
	1055	#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
	1056	#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
	1057	#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
	1058
	1059	#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
	1060	#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
	1061
	1062	#define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
	1063	#define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
	1064
	1065	#define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
	1066	#define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
	1067
	1068	#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
	1069	#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
	1070	/* 0x30 - 0x3f Unused Read only registers */
	1071
	1072	/************************************************************************************************/
	1073	/* EMU1010m HANA Destinations */
	1074	/************************************************************************************************/
	1075	#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1076	#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1077	#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1078	#define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1079	#define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1080	#define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1081	#define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1082	#define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1083	#define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1084	#define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1085	#define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1086	#define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1087	#define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1088	#define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1089	#define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1090	#define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
	1091	#define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
	1092	#define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
	1093	#define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
	1094	#define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
	1095	#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
	1096	#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
	1097	#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
	1098	#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
	1099	#define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
	1100	#define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
	1101	#define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
	1102	#define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
	1103	#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
	1104	#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
	1105	#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
	1106	#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
	1107	#define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
	1108	#define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
	1109	#define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
	1110	#define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
	1111	#define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
	1112	#define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
	1113	#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
	1114	#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
	1115	#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
	1116	#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
	1117	#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
	1118	#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
	1119	#define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
	1120	#define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
	1121	#define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
	1122	#define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
	1123	#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
	1124	#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
	1125	#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
	1126	#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
	1127	#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
	1128	#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */<